hardConceptDesignMidSeniorStaff
Why is one flip-flop not enough to bring a signal into another clock domain?
A flop sampling a signal that changes near its clock edge can go metastable and hold an invalid level for an unbounded time. A second flop gives it a full period to settle, which fixes metastability but not cycle alignment, so a multi-bit bus needs a handshake or an asynchronous FIFO rather than a synchroniser per bit.
7 min readUpdated 2026-08-15
Answer
Short answer
One flip-flop is not enough for a clock-domain crossing because a signal sampled near the clock edge can go metastable and feed invalid levels into logic. A two-flop synchronizer gives a single-bit level time to settle, but buses, pulses, and ordered data need handshakes, Gray-coded pointers, or asynchronous FIFOs.
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Likely follow-ups
- Why are the pointers of an asynchronous FIFO Gray coded rather than binary?
- How would you get a single-cycle pulse from a fast domain safely into a slower one?
- What goes wrong if the output of the first synchroniser flop is used by any logic other than the second flop?
- How do you tell static timing analysis to stop reporting the path into the first synchroniser flop, and what have you asserted by doing so?
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