Hardware and silicon design fundamentals

Register transfer level describes hardware as a set of storage elements plus the combinational logic that computes what moves between them on each clock edge. You are not drawing gates and you are not writing a program: you are saying which registers exist and what value each one takes next. That level exists because it is the highest abstraction a synthesis tool can reliably turn into gates while still letting you control timing. Above it, behavioural descriptions leave too much to the tool to be predictable; below it, gate-level design is unmanageable at any realistic size. The consequence is that almost every hardware interview question is an RTL question in disguise.

The vocabulary is the first filter, and most of it names an artefact rather than an activity.

term            what it actually is
--------------  ----------------------------------------------------------
RTL             registers plus the logic between them, written in an HDL
netlist         instances of real cells and the connections between them
synthesis       RTL in, netlist out, under timing and area constraints
constraints     the clocks, and what the tool must achieve, stated formally
STA             static timing analysis, checking every path without vectors
place and route deciding where each cell sits and how wires connect them
DFT             extra logic added so the manufactured part can be tested
soft IP         a block delivered as RTL that you synthesise yourself
hard macro      a block delivered already implemented, placed as one object
bitstream       the configuration data that programs an FPGA
GDSII           the layout format handed to the foundry

Read the middle rows as a pipeline: RTL becomes a netlist, the netlist becomes a placed and routed layout, and the layout becomes either a mask set or, for an FPGA, a bitstream. Each stage has its own idea of delay, and the numbers get more trustworthy as you go down, which is why timing that looked fine after synthesis can fail after routing.

The distinction between soft IP and a hard macro is the one candidates most often blur. Soft IP arrives as source, so it adapts to your process and your constraints and competes with your logic for area. A hard macro arrives already built, so its timing and power are known but its shape is fixed and your floorplan has to accommodate it. Choosing between them is a real decision with a real cost either way.

The two words worth being precise about are constraints and STA. Constraints are your statement of intent, and STA is the tool checking the design against that statement. Neither has any idea what your circuit is supposed to do, which is why a design can be perfectly constrained, entirely clean in timing, and functionally wrong.

RTL is a description of behaviour written by a person: an adder is a plus sign, a register is an assignment inside a clocked block. A netlist is a structural list of specific cell instances and the nets connecting their pins, produced by synthesis. The netlist contains no arithmetic operators and no if statements, only cells from a library. The practical consequences are that a netlist is enormous and unreadable by comparison, that it is tied to one target technology while the RTL is portable, and that any bug you find in a netlist has to be traced back to the RTL to be fixed, which is why keeping the two provably equivalent matters.

It is the palette synthesis is allowed to use: a set of small logic functions, flip-flops and buffers, each already laid out, each characterised for delay, output slew, input capacitance and power under a range of conditions. Cells in a library share a fixed height so they can be placed in rows, which is what makes automatic placement possible at all. The characterisation is what timing analysis actually reads, so the library is the bridge between a logical design and physical reality. A library usually offers the same function in several drive strengths and several threshold voltages, and choosing among them is how the tool trades delay against leakage.

Combinational logic goes into lookup tables, which are tiny memories addressed by the logic's inputs and whose contents are the truth table of the function you wanted. Any function of that many inputs costs exactly one lookup table, which is why FPGA area is counted in tables rather than gates. Around the tables sit flip-flops, dedicated arithmetic and memory blocks, and a configurable routing network of switches. The bitstream loaded at power-up sets the table contents and closes the routing switches. Everything about an FPGA's power and speed disadvantage follows from that structure, because the switches and unused resources exist in silicon regardless.

It states the things the tool cannot infer: which nets are clocks and at what period, how much uncertainty to allow on each, when inputs arrive relative to a clock and when outputs are needed, which paths are between unrelated clocks and should not be compared, and which paths are allowed more than one cycle. Everything the tool optimises for comes from that file, so an unconstrained clock is not optimised at all rather than optimised loosely. This is why reviewing constraints is as important as reviewing RTL, and why a clean timing report from a thin constraint file means nothing.

Fan-out is the number of inputs a single output drives. Each load adds capacitance, and a driver charging more capacitance switches more slowly, so a high fan-out net is slow and its slow transition degrades the timing of everything it feeds. Implementation tools deal with it by increasing the driver's strength or by replicating the driver and splitting the loads, which costs area and power. It matters in interviews because it is the mechanism behind advice that otherwise sounds arbitrary: a control signal broadcast to hundreds of places, or a reset distributed to every flop, needs a buffer tree in the same way a clock does.